1. Field of the Invention
The present invention generally relates to a process of generating test patterns for the functional verification of integrated circuit hardware designs and, more particularly, to testing external interrupts of a pipelined or super scalar processor wherein multiple instructions are loaded simultaneously for pipelined and/or simultaneous processing.
2. Description of the Prior Art
The present invention is an improvement on the process disclosed in U.S. Pat. No. 5,202,889 to Aharon et al. and assigned to a common assignee with this application. That patent discloses a dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs. Verification is performed by executing the test patterns on a design model in a sequence of steps. While the process in the Aharon et al. patent is effective for most integrated circuit testing, modern microprocessor design present some problems due to their complex designs.
Processor architectures allow for external interrupts. When a external interrupt is presented, the processor serves the interrupt by stopping the execution of its current instruction stream and branching to a predefined address, from which execution resumes. The processor also allows the software to return from the interrupt; i.e., to branch back and continue execution of its original instruction stream.
External interrupts are asynchronous; that is, they can be presented to the processor at any time. In addition, the latest microprocessor designs are pipelined and super scalar processors in which instructions may be executed out of their original order. When an external interrupt is presented, the processor may first complete the execution of the instructions which have already been fetched or which are in some stages of execution before it serves the interrupt.
Verification of processor behavior is carried out by simulation of test programs. Such test programs can be generated automatically by test generation tools such as Random Test Program Generators (RTPGs), which generate tests very efficiently. These generators also use reference models of the processor architecture to predict the expected results of the test after execution of its instructions. The test programs are run through a model of the design realization, which is referred to as the design simulator, and the actual results of the tests are compared against those predicted in the tests.
Automatic test generation tools, such as RTPGs, use reference models of the processor in order to predict the results of the tests they generate. For practical reasons, these models are based on the functional specification of the processor as defined in its architecture book and lack the specific knowledge of the internal states and actual timing. Such reference models cannot precisely predict when the external interrupt presented to the processor may happen. As a result, in tests which present external interrupts to the processor, the results may be unpredictable.
The alternative methods for automatic test generation are very inefficient. Therefore, it is important to solve the unpredictable result problem. This may be simply done by one of the following solutions:
1. Build the test in such a way that the precise location of the interrupt service has no effect on the test results. For example, only no-op instructions are incorporated in the range where the interrupt is expected to be serviced. PA1 2. Add instructions to the test which override the resources with unknown values.
These two solutions alone provide poor verification. The first limits significantly the scope of the tests where an external interrupt may be presented to the processor. In the verification process, any function should be tested under a range of conditions as wide as possible. The second solution causes resources which are set by the external interrupt mechanism to be masked and, as a result, if any of them is set to an incorrect value, it will not be reflected by incorrect results of the test.